In communication systems, the term “front-end” originally described the analog portion of a receiver or transmitter in proximity with the antenna. The front-end delivered an analog signal at an intermediate frequency (IF) to a back-end for digital processing. More recently, the term “front-end” has been extended to include some of the signal conditioning previously performed in the analog domain to digital processing components in more recent terminal or base-station systems.
A digital front end (DFE) is now a generic term for the circuitry between the BB processor and analog baseband/RF circuits. In the receiver, the DFE comprises the components that process the RF demodulated digitized signal, which may or may not contain an intermediate frequency (depending on whether the receiver is zero IF or non-zero IF). On the receiver side, the DFE extracts from the digital IF signal different channels (GSM, WCDMA, LTE or a combination of these technologies) at various IF frequencies digitally (operation used to be performed in the analog domain in previous generation systems).
In the transmitter, the DFE comprises the components that process the baseband signal for various channels in the digital domain and provide an up-converted digital signal. This up-converted signal may further undergo additional signal conditioning such as crest factor reduction and digital pre-distortion of RF power amplifier non-linear response, and is finally applied to a digital-to-analog converter (DAC).
A digital front end is typically implemented using hardwired logic due to the high sampling rates of the above mentioned multi-carrier multi-standard radio signals. While such hardware-based DFE techniques effectively process a communication signal, they suffer from a number of limitations, which if overcome, could further improve the efficiency and flexibility of DFE systems. For example, existing hardware-based DFE techniques lack flexibility and it is expensive, time consuming and challenging to modify the DFE design for a new RF design, as design of a DFE ASIC (Application Specific Integrated Circuit) is costly and time consuming (often a cycle of two years).
A number of techniques have been proposed or suggested for implementing portions of a DFE system in software. For example, portions of the DFE are implemented on a field-programmable gate array (FPGA) while other portions of the DFE are hardwired and other portions implemented in an ASIC. FPGAs contain programmable logic components called “logic blocks.” FPGA-based techniques, however, are prohibitive in terms of cost and power consumption.
Implementation of various DFE functions in software is possible. However, for existing sampling rates of hundreds of Megahertz, for example, a real-time DFE software implementation is not achievable on standard digital signal processors or even vector processors. A need therefore exists for efficient software-based DFE techniques.